1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device that can operate in a self refresh mode.
2. Description of the Background Art
In the field of semiconductor memory devices, the data retain time for retaining data written in a memory cell has become shorter as the integration density of semiconductor memory devices, particularly a dynamic RAM (referred to as DRAM hereinafter), is increased.
The increased scale of integration of the DRAM results in reduction of the capacitance per se of the memory cell capacitor, so that the effect of leakage current and the like that destroys the retain data can no longer be neglected.
In a DRAM, the operation of rewriting the retain data into each memory cell again, i.e., the refresh operation, must be carried at a constant interval.
Degradation in the data retain time of a memory cell means that the cycle time period of carrying out a refresh operation must be shortened. In other words, the number of refresh operations carried out within a constant time period is increased. This will cause greater power to be consumed.
When a DRAM is operated in a data retain mode in which backup is implemented by a battery, the refresh address and refresh actuation signal are generated within the DRAM to carry out a refresh operation. This is called a self refresh operation.
However, the potential level of the pair of bit lines BL and /BL connected to a memory cell belonging to a corresponding row in a memory cell array is generally precharged to 1/2 the internal power supply potential Vcca when the word line provided for every row of memory cells is inactive.
More specifically, a structure is provided in which readout can be carried out equally for data of an H level (logical high) or an L level (logical low) from a memory cell after a word line WL is activated since the potential level of bit lines BL and /BL is precharged to the potential of 1/2 Vcca.
This operation of precharging the potential level of the bit line pair to the level of 1/2 Vcca is also carried out in the above-described self refresh mode. In a self refresh mode, the refresh cycle is set longer than that of a normal operation to reduce the refresh operating current for a lower power consumption.
In other words, the cycle of a self refresh operation is determined relative to the refresh characteristic of a memory cell. If the cycle of the self refresh operation is set too long, the readout margin of an H level data is reduced. This will cause the error of a memory cell in which an H level is formerly written is altered to data of an L level.
It has become difficult to achieve sufficient capacitor capacitance since smaller memory cells are implemented to comply with the larger capacity of a DRAM. Accordingly, the refresh characteristic of a memory cell has become more severe. Under the present circumstances, it is difficult to reduce power consumption by increasing the cycle of the self refresh operation.
FIG. 10 is a schematic block diagram showing a structure of a conventional DRAM 2000.
Referring to FIG. 10, DRAM 2000 includes control signal input terminals 1002-1006, an address signal input terminal group 1008, a data signal input terminal group 1016, a ground terminal line 1018, and a power supply terminal 1020.
DRAM 2000 includes a clock generation circuit 1022, a row and column address buffer 1024, a row decoder 1026, a column decoder 1028, a memory mat 1023, a data input buffer 1040, and a data output buffer 1042. Memory mat 1032 includes a memory cell array 1034, and a sense amplifier+input/output control circuit 1038.
Clock generation circuit 1022 selects a predetermined operation mode according to a row address strobe signal EXT./RAS and a column address strobe signal EXT./CAS that are applied via control signal input terminals 1002 and 1004 to control the overall operation of DRAM 2000.
Row and column address buffer 1024 generates row address signals RA0-RAi and column address signals CA0-CAi according to externally applied address signals A0-Ai (where i is a natural number) via address signal input terminal group 1008. The generated signals RA0-RAi and CA0-CAi are provided to row decoder 1026 and column decoder 1028, respectively.
Memory mat 1032 includes a plurality of memory cells. Each memory cell stores data of one bit. Each memory cell is arranged at a predetermined address determined by the row address and column address.
Row decoder 1026 specifies a column address of memory cell array 1034. Sense amplifier+input/output control circuit 1038 connects the memory cell addressed by row decoder 1026 and column decoder 1028 to one end of a data signal input/output line pair IOP. Data signal input/output line pair IOP has the other end connected to data input buffer 1040 and data output buffer 1048.
In a writing mode, data input buffer 1040 responds to an external signal EXT./WE applied via signal control input terminal 1006 for providing the data input through data signal input terminal group 1016 to a selected memory cell via data signal input/output line pair IOP.
In a readout mode, data output buffer 1042 provides the data read out from a selected memory cell to data input/output terminal group 1016.
Power supply circuit 1050 receives external power supply potential Vcc and ground potential Vss to supply various internal power supply potentials required for an operation of DRAM 2000.
More specifically, power supply circuit 1050 includes an internal power supply circuit 1054 receiving an external power supply potential Vcc and ground potential Vss for providing internal power supply potentials Vcca and Vccp which are down-converted version of external power supply potential Vcc, and a boosted potential Vpp (Vcca&lt;Vccp&lt;Vcc&lt;Vpp), and a precharge potential generation circuit 1052 for supplying a precharge potential Vb1 corresponding to a bit line pair included in memory cell array 1034.
The internal power supply potential Vcca is supplied to memory cells. The internal power supply potential Vccp is supplied to the peripheral circuitry of DRAM 2000.
FIG. 11 is a circuit diagram showing a structure of precharge potential generation circuit 1052 in DRAM 2000 of FIG. 10.
Precharge potential generation circuit 1052 has its operation activated in response to activation of a signal /ACT (transition to an L level) from clock generation circuit 1022.
Precharge potential generation circuit 1052 includes a P channel MOS transistor 5102 receiving internal power supply potential Vcca at its source and rendered conductive according to activation of signal /ACT, a resistor 5104 and an N channel MOS transistor 5106 connected in series between a drain of P channel MOS transistor 5102 and a node Nn, and a resistor 5108 and an N channel MOS transistor 5110 connected in series between node Nn and ground potential.
N channel MOS transistor 5106 and N channel MOS transistor 5110 are diode-connected so that respective internal power supply potentials Vcca are in the forward direction towards the ground potential.
Precharge potential generation circuit 1052 further includes a P channel MOS transistor 5112 and a resistor 5114 connected in series between a drain of P channel MOS transistor 5102 and a node Np, and a P channel MOS transistor 516 and a resistor 5188 connected in series between node Np and ground potential.
P channel MOS transistor 5112 and P channel MOS transistor 5116 are diode-connected so that respective internal power supply potentials Vcca are in the forward direction towards the ground potential.
Precharge potential generation circuit 1052 further includes an N channel MOS transistor 5120 and a P channel MOS transistor 5112 connected in series between internal power supply potential Vcca and ground potential via a node Nc.
N channel MOS transistor 5120 has its gate receive a gate potential of N channel MOS transistor 5106. P channel MOS transistor 5122 has its gate receive a gate potential of P channel MOS transistor 5116.
Here, it is assumed that the resistance of resistors 5104 and 5108 and the resistance of resistors 5114 and 5118 are set to be respectively equal to each other.
Also, it is assumed that the characteristics of N channel MOS transistors 5106, 5110 and 5120 and the characteristics of P channel MOS transistors 5112, 5116 and 5122 are respectively set equal.
Therefore, the potential level of node N2 is 1/2 internal power supply potential Vcca. In other words, the gate potential of N channel MOS transistor 5106 is biased so that the source attains the potential level of node Nn.
Similarly, the potential level of node Np is 1/2 internal power supply potential Vcca. In other words, the gate potential of P channel MOS transistor 5116 is biased so that the source attains the potential level of node Np.
More specifically, N channel MOS transistor 5120 and P channel MOS transistor 5122 have their gates biased so that the potential level of respective connection nodes Nc is 1/2 internal power supply potential Vcca.
Thus, control is provided so that the potential of node Nc is 1/2 internal power supply potential Vcca.
This potential level of 1/2 internal power supply potential Vcca is supplied as the precharge potential level VBL of the bit line pair.
FIG. 12 is a circuit block diagram showing in detail a structure of one memory cell column with a portion omitted according to the structure of DRAM 2000 shown in FIG. 10.
For the sake of simplification, a structure is provided in which only a memory cell MC1 is connected to bit line BL and only a memory cell MC2 is connected to bit line /BL in FIG. 12.
Memory cell MC1 includes a memory cell transistor MT1 and a memory cell capacitor CP1.
Cell plate potential Vcp from power supply circuit 1050 is supplied to one terminal of memory cell capacitor Cp1.
The connection between the other terminal of memory cell capacitor CP1 and a corresponding bit line is opened/closed by a memory cell transistor MT1 that has its gate potential level controlled by a word line WLn.
Memory cell MC2 basically has a structure similar to that of memory cell MC1.
Here, the potential level of 1/2 Vcca is generally employed as cell plate potential Vcp.
A transistor TQ3 having its gate potential level controlled by a bit line equalize signal BLEQ is provided between bit lines BL and /BL. A transistor TQ1 is connected between a supply interconnection LVB of bit line precharge potential VBL and bit line BL. Also, a transistor TQ2 is connected between interconnection LVB and bit line /BL. Transistors TQ1 and TQ2 have their gate potentials controlled by signal BLEQ.
When signal BLEQ is rendered active under control of clock generation circuit 1022, the potentials of bit lines BL and /BL are equalized to an equal value by transistor TQ3. This potential will be maintained at the value of bit line precharge potential V.sub.BL.
Following this equalize operation of a bit line pair, a data readout operation or a self refresh operation is carried out.
As disclosed in Japanese Patent Laying-Open No. 7-85658, the refresh characteristic of a memory cell can be improved by setting the value of this precharge potential level V.sub.BL lower than that of a normal operation mode in a self refresh operation mode.
The reason thereof will be described briefly hereinafter.
More specifically, the relationship between the readout margin of an H level data and bit line precharge potential V.sub.BL in a readout operation is evaluated as set forth in the following.
It is assumed that the internal power supply potential supplied to a memory cell array is Vcca, the bit line floating capacitance accompanying a bit line is Cb, the capacitance of a memory cell capacitor is Cs, and the cell plate potential is Vcp.
When an L level data is written into a memory cell capacitor, the charge Q.sub.SL accumulated in the memory cell capacitor is represented by the following equation. EQU Q.sub.SL =-CsVCP . . . (1)
When an H level data is written, charge Q.sub.SH accumulated in the memory cell capacitor is represented by the following equation. EQU Q.sub.SH =Cs(Vcca-Vcp) . . . (2)
Charge Qb accumulated in a precharged bit line is represented by the following equation. EQU Qb=CbV.sub.BL (3)
According to the above relationship, the amount of change in the bit line voltage (read out voltage .DELTA.V) at conduction of a memory cell transistor MT (transfer gate) when data of an L level is stored in a memory cell capacitor is expressed as below. EQU .DELTA.V.sub.L =-V.sub.BL /(1+Cb/Cs) (4)
When data of an H level is stored in the memory cell capacitor, the amount of change in the bit line voltage is represented as below. EQU .DELTA.V.sub.H =(Vcc-V.sub.BL)/(1+Cb/Cs) (5)
Referring to equations (1)-(5), the read out voltage .DELTA.V.sub.L of an L level is equal to the absolute value of readout voltage .DELTA.V.sub.H at the read out of an H level data when bit line precharge potential V.sub.BL is 1/2 Vcca. Therefore, the following relationship is established. EQU .vertline..DELTA.V.sub.L .vertline.=.vertline..DELTA.V.sub.H .vertline.(6)
When bit line precharge potential V.sub.BL is smaller than internal power supply potential 1/2 Vcca, the following relationship is established. EQU .vertline..DELTA.V.sub.L .vertline.&lt;.DELTA.V.sub.H .vertline.(7)
In other words, the margin in the read out operation of an H level is increased by setting bit line precharge potential V.sub.BL lower than 1/2 internal power supply potential Vcca.
Since reduction in the read out margin due to a smaller capacitance of a memory cell capacitor generally implies degradation in the margin in reading out data of an H level, the margin in a read out operation is increased by the lower bit line precharge potential V.sub.BL.
This means that the self refresh cycle time can be increased in a self refresh mode operation. More specifically, power consumption can be reduced.
However, it is difficult to achieve sufficient reduction in power consumption by just setting bit line precharge potential V.sub.BL smaller than 1/2 internal power supply potential Vcca.
FIG. 13 is a timing chart for describing the potential level of a bit line pair over time in a readout operation or a self refresh operation.
In the timing chart of FIG. 13, the dotted line corresponds to bit line precharge potential V.sub.BL at the level of 1/2 internal power supply potential Vcca, and the solid line corresponds to bit line precharge potential V.sub.BL at a level lower than 1/2 internal power supply potential Vcca.
As described above, the readout margin itself for data of an H level can be increased by setting bit line precharge potential V.sub.BL lower than 1/2 internal power supply potential Vcca. However, the potential level of the bit line that swings to the H level, for example bit line BL, shows a transition from the level of the precharge potential V.sub.BL (Vcca/2) to the level of internal power supply potential Vcca.
This means that a greater charging current must be applied to bit line BL than the case where bit line precharge potential V.sub.BL is at the level of potential Vcca/2.
There is a possibility that the power consumption reduction during self refresh is not sufficient even when the readout margin is increased by setting bit line precharge potential V.sub.BL lower than 1/1 internal power supply potential Vcca to allow the self refresh cycle time to be increased.